Internal PS/2 Port

[benryves]

The poor old AT routines have difficulty keeping up at the 11kHz or so of the AT protocol; I doubt they'd be able to keep up with USB speeds. A software USB solution is probably not going to get very far.

USB peripherals tend to have both a USB and AT controller inside them, and will switch to whichever is appropriate when running. This is why you can plug a USB peripheral into an AT port but cannot plug an AT peripheral into a USB port without a box of fancy electronics between them.

[KermMartian]

I think that the USB routines might wait for ack bits though, so it's possible that it might indeed be feasible...

[benryves]

Hm, really? I'm not sure at all how the physical side works. I'll have to look into it.

[KermMartian]

Reading, here's what I see:
>>half-duplex: only one direction at a time
>>every device has at least one endpoint that acts as a send/rec buffer
>>The lowest-speed data rate is a nominal 1.5Mb (bits) per second, but I need to find more on the electrical protocol....

Ah, here's some good stuff:

USB as its name would suggest is a serial bus. It uses 4 shielded wires of which two are power (+5v & GND). The remaining two are twisted pair differential data signals. It uses a NRZI (Non Return to Zero Invert) encoding scheme to send data with a sync field to synchronise the host and receiver clocks.

Wow, complex O.o

As we have discussed, USB uses a differential transmission pair for data. This is encoded using NRZI and is bit stuffed to ensure adequate transitions in the data stream. On low and full speed devices, a differential ‘1’ is transmitted by pulling D+ over 2.8V with a 15K ohm resistor pulled to ground and D- under 0.3V with a 1.5K ohm resistor pulled to 3.6V. A differential ‘0’ on the other hand is a D- greater than 2.8V and a D+ less than 0.3V with the same appropriate pull down/up resistors.

The receiver defines a differential ‘1’ as D+ 200mV greater than D- and a differential ‘0’ as D+ 200mV less than D-. The polarity of the signal is inverted depending on the speed of the bus. Therefore the terms ‘J’ and ‘K’ states are used in signifying the logic levels. In low speed a ‘J’ state is a differential 0. In high speed a ‘J’ state is a differential 1.

USB transceivers will have both differential and single ended outputs. Certain bus states are indicated by single ended signals on D+, D- or both. For example a single ended zero or SE0 can be used to signify a device reset if held for more than 10mS. A SE0 is generated by holding both D- and D+ low (< 0.3V). Single ended and differential outputs are important to note if you are using a transceiver and FPGA as your USB device. You cannot get away with sampling just the differential output

.

So yeah, the bottom line is that this would be rather impractical.